This invention relates to a semiconductor integrated circuit (IC) element having three-dimensionally stacked active layers and more particularly to such an element with improved reliability and degree of integration, having throughholes for efficient wiring and miniaturized areas with simplified design. The present invention further relates to a semiconductor IC element including a test circuit in redundant structure such that the functions originally intended for the element can be tested reliably.
With the recent progress in miniaturization technologies, many kinds of semiconductor memory circuit elements such as dynamic random-access memories are becoming highly integrated. Memory cells which occupy most of the areas of semiconductor IC elements of a dynamic random-access memory are now of a one-transistor one-capacitor structure and such memory cells are also becoming smaller. With the miniaturization of such memory cells, many ideas have been proposed to keep the capacitance of cell capacitors reasonably large. Grooved and stacked capacitors have thus been considered in order to increase the effective area of a cell capacitor. Since the capacitance of a cell capacitor for each memory cell must be maintained at a certain level, the degree of integration can be increased only if the element area can be increased accordingly so long as the same miniaturization technology is employed.
Another problem to be considered relates to the production yield which tends to go down as the degree of integration is increased, thus adversely affecting the reliability of the products. As a countermeasure to this problem, use of redundant circuits has been considered. In the case of a semiconductor memory element, for example, spare memory cells and decoders have been incorporated as redundant circuits in order to improve the yield. Because of the space limitation, however, such redundant circuits cannot be incorporated freely. Moreover, redundant circuits which are manufactured by the same process used for the original circuit are equally likely to be defective. In other words, efficacy of redundant circuits are determined by their number and their individual reliability, but since only a limited number of redundant circuits can be used because of the aforementioned space limitation, there is also a limit to the improvement in the yield.
A still further problem related to such elements is the testing of their operational functions. Such function tests are carried out on produced elements, for example, for the development of new products. Recently, semiconductor IC elements with a simple function test circuit have been considered in order to reduce the time required for such testing. If such a test circuit itself is defective, however, the user would consider an otherwise acceptable product to be defective, or not testable. In such a situation, the product will have to be directly tested by some other means. If such defects are frequent, the test circuits which were incorporated for the purpose of reducing the testing time lose their reason for existence. Moreover, since the available area on each element is limited as mentioned above, it is not practical to incorporate a test circuit which is large enough to be able to test too many functions of the element. In short, the time required for testing cannot be reduced significantly.
A still another problem to be considered relates to the technology of forming a recrystallized active area by melting polycrystalline silicon by irradiation. At the present time, it is not possible to form the entire surface of an element as a uniformly oriented recrystallized active area like a single crystalline silicon substrate. As shown in FIGS. 13A, 13B and 13C, crystalline granular interfaces are inevitably formed where single crystalline areas with different surface orientations join together. FIGS. 13A, 13B and 13C show conceptually an active layer of SOI (silicon on insulator) structure grown by melting polycrystalline silicon by irradiation on an insulative layer. FIG. 13A is its plan view, FIG. 13B is its sectional view taken along the line A-A' of FIG. 13A and FIG. 13C is its perspective view. In these figures, numerals 201, 202 and 203 are recrystallized areas where transistors can be formed (hereinafter referred to as active element areas) and numeral 204 indicates an insulative layer. When the areas 201, 202 and 203 are formed by melting polycrystalline silicon by irradiation, the silicon begins to harden from the center of the irradiating beam and hence the surface orientations are not necessarily uniform. As a result, crystalline granular interfaces 205 are formed. Numerals 206, 207, 208 and 209 indicate areas where crystalline granular interfaces are expected to be present. It is not desirable to place channels of MOS transistors and the like in such an area. Although they should ideally be placed in recrystallized active element areas, this causes to limit the areas where transistors can be disposed and hence the degree of integration.